In a synchronous computer system, data is transmitted between latches, registers, other state devices or other subsystems. If the data can potentially change every cycle, the system is called "full bandwidth". In prior synchronous computer systems, the time available to transmit full bandwidth data between devices does not exceed one cycle time minus the clock skew.
In very fast cycle time synchronous computer systems, the one cycle time minus the clock skew window may be inadequate to cover the delay in the data path between devices. In such systems, proper operation cannot be guaranteed. Thus, there is a need to successfully address and solve the problem of transmitting data in high speed synchronous computer systems.